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At IDF last year Intel's Justin Rattner demonstrated a 32nm test chip based on Intel's original Pentium architecture that could operate near its threshold voltage. The power consumption of the test chip was so low that the demo was powered by a small solar panel. A transistor's threshold voltage is the minimum voltage applied to the gate for current to flow. The logical on state is typically mapped to a voltage much higher than the threshold voltage to ensure reliable and predictable operation. The non-linear relationship between power and voltage makes operating at lower voltages, especially those near the threshold very interesting.

At this year's ISSCC Intel is presenting details of a number of NTV (near threshold voltage) research projects. For starters, Intel is sharing more details on Claremont - the 32nm NTV Pentium processor demonstrated at IDF. At 3MHz Claremont can operate at 280mV and scale up to 1.2V at 915MHz. Minimum power for Claremont is a meager 2mW.

Intel is also sharing details of a 22nm NTV SIMD engine for use in processor graphics. Given Intel's new focus on improving processor graphics performance, the fact that we're seeing more Intel driven research around GPU technologies isn't surprising. It's also important to point out that Intel needs the experience in building NTV circuits for both CPUs and GPUs if this technology is ever to make it into an actual product. NTV operation grants much better power efficiency where possible, making eventual productization very desirable.

Gallery: Intel at ISSCC '12: More Research into Near Threshold Voltage

At IDF last year Intel's Justin Rattner demonstrated a 32nm test chip based on Intel's original Pentium architecture that could operate near its threshold voltage. The power consumption of the test chip was so low that the demo was powered by a small solar panel. A transistor's threshold voltage is the minimum voltage applied to the gate for current to flow. The logical on state is typically mapped to a voltage much higher than the threshold voltage to ensure reliable and predictable operation. The non-linear relationship between power and voltage makes operating at lower voltages, especially those near the threshold very interesting.

At this year's ISSCC Intel is presenting details of a number of NTV (near threshold voltage) research projects. For starters, Intel is sharing more details on Claremont - the 32nm NTV Pentium processor demonstrated at IDF. At 3MHz Claremont can operate at 280mV and scale up to 1.2V at 915MHz. Minimum power for Claremont is a meager 2mW.

Intel is also sharing details of a 22nm NTV SIMD engine for use in processor graphics. Given Intel's new focus on improving processor graphics performance, the fact that we're seeing more Intel driven research around GPU technologies isn't surprising. It's also important to point out that Intel needs the experience in building NTV circuits for both CPUs and GPUs if this technology is ever to make it into an actual product. NTV operation grants much better power efficiency where possible, making eventual productization very desirable.

Gallery: Intel at ISSCC '12: More Research into Near Threshold Voltage

This week is the annual International Solid-State Circuits Conference (ISSCC) where chip companies from all walks of life present papers documenting everything from shipping architectures to future research projects. Intel has always had a large presence at the conference and this year is no different. I'm still trying to get my hands on some of the actual papers being presented but Intel invited some press to a pre-brief on the high level announcements from the conference. 

One such announcement is a test SoC called Rosepoint. It's a 32nm dual-core Atom SoC with an integrated WiFi transceiver. Despite the high levels of integration we see in smartphone SoCs, WiFi is typically serviced by an external combo chip that integrates WiFi and Bluetooth among other radio technologies. Rosepoint brings the WiFi functionality on-die. The name of the game in the mobile SoC space is integration, making Rosepoint a research project with significant real world implications.

Integration is nothing new of course. AMD, Intel, NVIDIA, Qualcomm, TI and all of the others playing in the SoC space have been slowly integrating more functionality on-die over the past decade. Intel claims the difficulty in bringing WiFi on-die is mitigating interference between the RF transceiver and the rest of the SoC. The details of Rosepoint's architecture and how Intel was able to reliably integrate the two are likely described in the ISSCC paper. If I can get my hands on it I'll see about updating this post.

Rosepoint is important because of Intel's dillema as it enters the smartphone SoC space. Most high-end smartphone SoCs sell in the $14 - $25 range, a significant reduction compared to the $50 - $1000 Intel is used to getting for CPUs. Even if you look at smartphone-sized x86 CPUs, Intel can typically get somewhere between $50 - $100 for the CPU. Then add another $20 - $30 for the chipset and margins start looking very nice. Intel can't guarantee > 60% margins selling ~$20 smartphone SoCs. At the same time, Intel based smartphones wouldn't sell very well if they were significantly more expensive than the competition. This puts Intel in a difficult position: settle for lower margins (and upset wallstreet) or figure out a way to offer more value by integrating other parts of the bill of materials. 

Offering and integrating radios where possible is clearly one step, although we'll likely see integrated cellular baseband before we see on-die WiFi. Intel's recent restructuring left the new mobile & comms group with a mandate to deliver an ultra low-power WiFi solution that could work in a smartphone. The first Intel based WiFi in smartphones will begin as a discrete chip but it's clear that integration is on Intel's mind.  The other options for Intel to bring some of that precious BOM in house is to offer reference platforms and/or use software as a differentiator.

In the early days Intel would just sell a CPU and rely on third parties for the rest of the chips on the motherboard. Then came Centrino and the new platform-centric Intel. Expect to see a similar effort in smartphones.

Intel has finally filled out the Sandy Bridge E lineup by releasing the Core i7-3820. The initial Sandy Bridge E lineup launched back in November 2011 and it consisted of two SKUs, the i7-3960X and i7-3930K. While the i7-3820 wasn't released until this week, we reviewed it over a month ago, so head there for a longer analysis. The table below summarizes the current Sandy Bridge E lineup:

The short summary is that i7-3820 is Sandy Bridge E on a budget. In terms of CPU performance and price, it's equivalent to the i7-2600(K) but provides higher I/O performance due to the quad-channel memory and 40 PCIe 3.0 lanes. Anand summed it up nicely in his review, so we'll just repost here.

There are three reasons why you'd want the Core i7-3820:

1. You need PCIe 3.0 today and/or you need more PCIe lanes than a Core i7-2600K can provide.
2. You need tons of memory bandwidth for a particular application.
3. You want a 2600K but you need a platform that can support more memory (32GB+).

So in general, most users will be better off with a LGA 1155 based platform. While the i7-3820 is actually cheaper than the i7-2600K, the total price of the platform is not. LGA 1155 based motherboards go for as little as ~$50 (e.g. Gigabyte GA-H61M-DS2). If you want more features such as Intel Rapid Storage Technology, you can get a Z68 based motherboard for around $90 (e.g. ASRock Z68M/USB3). In contrast, the cheapest LGA 2011 based motherboard starts at $210. Unless you benefit from the extra features that Sandy Bridge E offers, your money is better spent else (e.g. on an SSD).

AMD has quietly released two Athlon II X4 CPUs, the 638 and 641. These are based on Llano (i.e. Stars+/K10.5 architecture) but lack an integrated GPU. The socket is still FM1, just like in normal Llano CPUs. Here's a quick rundown of the chips.

There is nothing extraordinaty in these chips. We are looking at relatively low-end SKUs in terms of price and performance. It's good to keep in mind that a discrete GPU is needed because these SKUs lack integrated graphics, so that will potentially raise the total system price.

The usage of the Athlon II brand with Llano isn't actually a new thing as the first such SKU, Athlon II X4 631, launched back in August. This is quite similar to what Intel is doing; AMD is saving the A4, A6, A8, and FX brands (their rough equivalent of Intel's Core i3/i5/i7) for midrange and high-end chips, and reusing their older Sempron and Athlon brand names (e.g. Intel's Celeron and Pentium) with lower-end SKUs.

A theme of the new AMD is modularity. We've of course heard this before as it has always been a goal of AMD's to bring to market more modular, configurable designs, however this time the rhetoric is a lot more serious. In our earlier coverage we talked about future AMD SoCs allowing for a combination of AMD x86 CPU, GPU and 3rd party IP blocks. What AMD didn't mention during its Financial Analyst Day presentations however was how it would enable this pick-and-choose modular design. The secret, as it turns out, is in a new modular fabric that AMD is designing. 

It will take AMD until 2014 - 2015 to actually have the first, fully functional modular fabric in an SoC, but that's the goal. Being able to design a foundation that can interface with multiple buses (e.g. PCIe, HT, AMBA for ARM, etc...) will enable AMD to build more modular SoCs. 

With the fabric created, AMD can also change the way it does chip design. Today APU designs are seen from start to finish. Teams work on the various components of the design, but those components are viewed as a part of the whole, not as independents. E.g. the GPU portion of Trinity is worked on as Trinity's GPU, not a GPU block that will be re-used in other chips. Under the new AMD, teams will work on designing modular IP blocks without much focus on where they end up. You'll have teams that will work on a GPU block and simply move onto another GPU project after they're done.

Assuming AMD's new scalable SoC fabric is flexible enough, theoretically an APU designer could pick and choose from the various IP blocks and deliver a customized design that's decoupled from the individual blocks themselves. Similar to how you'll see an Imagination Technologies PowerVR SGX 540 in a variety of SoCs, AMD could build a GCN GPU block and use it in a variety of SoCs that address different markets. You can view AMD as having a broad portfolio of x86 and GPU cores and with this new SoC fabric it can mix and match those blocks as it sees fit. Furthermore, if the need arises, AMD could add in 3rd party IP where appropriate. 

We've actually heard of similar approaches to design from other companies in the SoC space, including Intel. With Atom Intel introduced a sea-of-FUBs (functional unit blocks) design methodology that leveraged more synthesized logic and modular blocks to reduce time to market and reduce feature creep. Atom also uses a fair amount of 3rd party IP (GPU, video encode/decode).

AMD's strategy makes a lot of sense. There's still a lot of execution that needs to happen before we get to the point where we can take modularity for granted, but the direction is sound.

We've been providing live coverage of AMD's 2012 Financial Analyst Day from Santa Clara today, but if you want a summary of the company's strategy under new CEO Rory Read you've come to the right place. Below you'll find links to everything we've published from AMD's FAD 2012:

AMD's Rory Read Outlines AMD's Future Strategy
AMD Outlines HSA Roadmap: Unified Memory for CPU/GPU in 2013, HSA GPUs in 2014 
AMD is Open to Integrating 3rd Party IP in Future SoCs
AMD's Financial Analyst Day 2012 - Mark Papermaster, SVP & CTO Presentation 
AMD: Flexible Around ISA
AMD Nods at Shorter Design Cycles, More Synthesized Designs
What AMD Views as Important: Tablets, Servers, Notebooks & GPUs
AMD & Compal Show Off 18mm Trinity Notebook 
AMD's 2012 - 2013 Client CPU/GPU/APU Roadmap Revealed 
AMD's 2012 - 2013 Server Roadmap: Abu Dhabi, Seoul & Delhi CPUs
AMD is Ambidextrous, Not Married to Any One Architecture, ARM in the Datacenter? 
AMD's Tablet Architectures: Hondo at 4.5W, Future Sub-2W SoC

Read on for our summary and analysis of AMD's new strategy.

In its client roadmap AMD revealed Hondo, a 4.5W APU with 1 - 2 low voltage Bobcat cores and an on-die DX11 GPU built on a 40nm process. Hondo will fit into Windows 8 tablets starting later this year. Going forward, AMD wants to get into the sub-2W market although we don't have a codename to associate with that power target. Mobile is very important to AMD going forward both in tablets and ultra thin notebooks and it looks like AMD is planning on building the architectures it needs to be successful there.

We've been hammering this point home all day, but AMD just mentioned it again. The company wants to be a solutions provider, one that's ambidextrous and not married to any one architecture. AMD is likely talking about ARM here and seems willing to offer both ARM and x86 based SoCs depending on the market segment/customer requirements.

What's important to note is that thus far AMD has talked about these ambidextrous solutions with respect to the datacenter and not client systems, and definitely not smartphones. If you were looking for AMD to get into the ARM based SoC race in phones, that's not what's going to happen. An AMD architected ARM based enterprise solution is interesting though. It's unclear to me what the main advantage of ARM would be there, particularly given that AMD has its own low power x86 core with Bobcat, but it's an interesting notion.

We've got a server roadmap update from AMD courtesy of its Financial Analyst Day here in Santa Clara, California. The changes to the 2012 - 2013 roadmap aren't all that startling. Obviously this year AMD delivers top to bottom Bulldozer based CPUs. Interlagos, which we've already reviewed, features between 4 and 16 Bulldozer cores (2 - 8 modules). There are 2 and 3 module variants as well: Zurich and Valencia, respectively. All three of these Bulldozer based CPUs fall in the Opteron 6200 line. 

Originally AMD had talked about introducing a new G2012 platform and delivering 10 & 20-core solutions called Sepang and Terramar. Those plans have been scrapped for the moment and what we get instead is a drop-in replacement for existing Opteron 6200 CPUs. 

Take the current 6200 lineup, upgrade the CPU cores to Piledriver and you get a high level look at AMD's near-term server strategy. The sockets remain the same, as do the core counts, but performance should go up. AMD hasn't given us any more detail as to what Piledriver fixes other than to say that it's a higher IPC version of Bulldozer.